Pinning Fault Mode Modeling for DWM Shifting

Extreme scaling for purposes of achieving higher density and lower energy continues to increase the probability memory faults. For domain wall (DW) memories, misalignment faults arise when aligning domains with access points. A previously understudied type shifting fault, a pinning fault may occur due non-uniform potential distribution caused by notches fabrication imperfections. This non-uniformity can pin during current-induced DW motion. paper provides model geometric variations varying width, depth, curvature notch, their impacts on critical shift current, study resulting impact rates systems. An in effective current 5% variation predicts rate order $10^{-8}$ per shift, which results mean-time-to-failure circa 2s system.